1. Field of the Invention
The present invention relates to a central processing unit (hereinafter abbreviated to a `CPU`) used in a system including a microprocessor and in a system including a sequencer, such as a DSP (Digital Signal Processor).
2. A CPU executes an operation according to a software program. The software program is a set of instructions and the operation is performed as a result of the instructions being executed.
Ordinarily, an instruction includes a combination of an operation (a type of the instruction) and an operand. The type of instruction indicates which operation the CPU should perform and the operand indicates data to be processed in the operation. Ordinarily, the data to be processed in the operation is often expressed using a location at which the data is stored in the operand. That is, actually, an operand may be information which is used for addressing the location of the data to be processed in the operation. There are various ways to indicate the location of data. Further, a number of operands included in a single instruction depends on a particular type of the instruction. For example, an operation instruction such as a logical sum OR, A.vertline.B.fwdarw.C, requires three operands A, B and C. In this case, it is preferable that a location of each of the three operands can be addressed without any restriction.
However, actually, there may be various restrictions on such addressing. For example, there may be a restriction concerning an instruction code length. If locations of three operands are individually addressed using operands, a total instruction code length including the operands is long. As a result, a software program including an instruction of the total instruction length has a large size, and a memory storing the software program should have a large storage capacity. Further, if an instruction of an instruction code length is long, a long time is required for reading and decoding the instruction and thus an efficiency of an operation may not be high. When each of the three operands has particular addressing to be performed therefor, a number of possible combinations of the three operands is the third power of a number of possible addressing manners for each data. If a number of types of instructions and number of combinations of operands are large, a number of combinations of the types of instructions and operands is very large.
The CPU has an internal software program integrated therein. Such an internal software program is used when the CPU analyzes an externally supplied software program and thus appropriately executes the externally supplied software program containing the above-described instructions. Such an internal software program is referred to as a microprogram. If a number of types of instructions and a number of combinations of operands are large, a number of combinations of the types of instructions and operands is very large, and the microprogram has a very large size accordingly. If the microprogram has a very large size, it may not be possible that the CPU has the microprogram integrated therein.
In order to reduce the number of combinations of operand addressing, a number of operands may be reduced to two from the three. Specifically, there is a method, referred to as a two operand method, in which, for example, in the logical sum OR, A.vertline.B.fwdarw.B. That is, in the above-mentioned expression A.vertline.B.fwdarw.C, the operand C is common with the operand B and thus A.vertline.B.fwdarw.B. An operand such as the operand C in this example is an operand which represents a result of the operation and is referred to as a destination operand. An operand such as the operand B in this example is an original operand and is referred to as a source operand. By this two operand method, addressing of operands can be completed only by addressing two operands such as those A and B in this example. Accordingly, in comparison to the case where -the operands are three, such as those A, B and C, a number of combinations of operand addressing can be reduced. Although the two operand method has some restrictions, this method is a general method and is used in many CPUs on the market.
In execution of an instruction by a CPU using the two operand method, there are three states: a source operand address calculation state in which an address of a source operand is calculated; a destination operand address calculation state in which an address of a destination operand is calculated; and a operation performance state in which an operation is performed. In the above-described example of the logical sum OR, A.vertline.B.fwdarw.B, the source operand address calculation state calculates an address of A, the destination operand address calculation state calculates an address of B, and the operation performance state performs the operation of A.vertline.B and then stores the result in B. Further, there may be various instructions such as that which does not require any operand addressing, and that which requires addressing of only one of the source and destination operands.
It is preferable that a CPU can smoothly execute various instructions according to a microprogram having a small size.